EG devices require thicker spacers to pass standard reliability requirements. Whereas thin spacers are desired on SG devices to maintain standard performance criteria. Typical dual RSD integration relies on additive NFET/PFET spacers to block unwanted epitaxial (epi) growth. However, the device with the thicker spacer often takes a performance hit. Specifically, a high RSD/gate capacitance degrades Fmax. Known approaches involve using multiple spacer materials to force RSD epi facet; sacrificing SG performance by using thicker spacers on all devices; or adding two additional spacers, a masking layer, and epi steps to support NFET and PFET EG devices. Another known approach involves forming a nitride/oxide spacer sandwich, which is difficult to control due to the use of several oxide consuming steps, e.g., multiple epi pre-cleans.
A need therefore exists for methodology enabling balanced SG performance and EG reliability with matched NFET/PFET spacer widths, methodology enabling formation of SG NFET, SG PGET, and EG NFET and PFET devices with different spacer thicknesses on FDSOI, and the resulting devices.